parallel processors造句
例句與造句
- content addressable parallel processor
內涵可尋址并行處理機 - amdahl s law governs the speedup of using parallel processors on a problem versus using only one serial processor
amdahl法則揭示了使用并行處理器來解決問題與只使用一個串行處理器來解決問題的加速比。 - because the performance of single microprocessor can " t be improved indefinitely due to the limitation of speed and machining technology of chips, so came the massive parallel processors system
而單處理器計算機系統(tǒng)由于處理器運算性能受限于芯片速度極限和加工工藝極限，不可能無限提高。于是超大規(guī)模并行處理系統(tǒng)應運而生。 - this design can provide a high-speed path to a set of sharc parallel array processor . between this parallel processor and an analog signal acquisition module, the designed system can realize real time transmission
本設計的目的在于為一套sharc并行處理陣列機提供高速的數據通道，使其能與模擬信號采集模塊進行實時的數據傳輸。 - edge is one of the important characteristics of image, and it also is the element of several research areas, like computer vision and pattern identification . cellular neural network ( cnn ) is a parallel processor
邊緣是圖像中重要的特征之一,是計算機視覺、模式識別等研究領域的重要基礎。細胞神經網絡(cnn)是一種并行處理器,在圖像處理上有很大的發(fā)展空間。 - It's difficult to find parallel processors in a sentence. 用parallel processors造句挺難的
- after analyzing the characteristic of the parallel processing system, some problems about design missile-carrying processing system are pointed out; network in the parallel processing system has become bottleneck and affect the performance of system, so the processing efficiency is analyzed in a multiprocessor system based on cluster-bus and some rules in designing the network in the multiprocessor system are brought out; genetic algorithm is used for scheduling in the multiprocessor system, and a scheduling algorithm is described to suit arbitrary number of tasks, unequal task processing time, arbitrary precedence relation among tasks and arbitrary number of parallel processor, so that the schedule length will be minimized; finally, an atr algorithm is mapped to a ring multiprocessor system, and a block diagram using dsp device is constructed . in chapter 4, the study is performed on real-time system hardware realization of atr . tms320c80 is selected as the kernel processor in multiprocessor system
為此，對一種由常用的dsp芯片組成的多處理器系統(tǒng)的處理器利用率進行了分析，提出了多處理器系統(tǒng)互連網絡設計的基本原則；本章使用遺傳算法作為實現多處理器調度的工具，提出了一種新的任務調度算法，該算法主要是為了解決在任務數任意、任務計算時間不相等、任務前趨關系任意、以及任務間存在通信和考慮任務存貯器要求的情況下，如何優(yōu)化任務在各個處理器上的分配和執(zhí)行順序，使得多處理器系統(tǒng)總的執(zhí)行時間最??；最后對一個目標識別算法進行了硬件實現優(yōu)化分析，根據分析結果，將算法映射到由dsp芯片組成的環(huán)形網絡連接的處理器拓撲結構上，得到了多處理器系統(tǒng)的原理框圖。 - on the basis of summarization of the simulating technology of sonar signal, the paper brings forward the mathematics models of radiate noises of ships and torpedo, and simulates in computer; tests the correctness of some pivotal methods through the simulation, on the basis of which, system scheme being brought out; a parallel processor with twelve sharcs, combining with parallel processing theory and topographic configuration, is used to realize the algorithm of noise simulation on the basis of research on optimum distribution of algorithm and method of embedment in real time; at last, gui, realized with vc + + language, is used to set parameters and control the whole parallel system flexibly and conveniently
本文在綜述聲納信號模擬技術的基礎上，首先提出艦船和魚雷輻射噪聲的仿真數學模型，并進行了計算機仿真實現；通過計算機仿真驗證了一些關鍵技術的正確性，并由此提出系統(tǒng)實時實現方案；構造了一個12個處理器的并行處理機?sharc陣列，結合并行處理理論和sharc陣列的拓撲結構研究了有關仿真算法的最優(yōu)分配及其嵌入整個聲納系統(tǒng)的方法，實時實現了噪聲模擬算法。最后，使用vc++語言編寫人機界面，靈活、方便地進行參數設置以及對整個并行處理系統(tǒng)進行控制。 - in this paper, real time torpedo homing system . which is based on adsp ? 2106x to be discussed . high speed signal parallel processor system is researched, it is made up of intel 80c186eb processor main board and adsp _ 2106x . it can be come true using this system for the accuracy parameter estimation of underwater target which moves on high velocity
本課題是以高速并行數字信號處理芯片adsp?2106x為核心，以intel80c186eb微處理器構成的cpu模塊為主控板，構成完整的高速并行數字信號處理機硬件系統(tǒng)，該硬件系統(tǒng)可以成功地實現現代魚雷自導的水下高速運動目標參量實時精估算法。 - finally discusses several class different multi-dsp extended architecture based on vvp platform . chapter 3 analyzes the significance of dynamic reconfiguration of multi-dsp parallel processing system, introduce run-time reconfiguration technique of fpga . with comparison of the common used dynamic communication network in parallel processor system, proposes the new dynamic reconfigurable multi-dsp system architecture based on run-time reconfigurable fpga
第三章分析了多dsp并行系統(tǒng)體系結構動態(tài)可重構的意義，介紹了fpga動態(tài)配置技術，比較了現有的一些多處理器動態(tài)互連的設計實現方法，在此基礎上，提出了利用局部動態(tài)重構fpga技術設計實現實時動態(tài)可重構多sharc功能系統(tǒng)的新方法。